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Digital Oscillator Circuit - Ensoniq 5503DOC
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Did you know that the DOC was not only used in the ancient Ensoniq machines but also as the heart of computer sound cards - and that it even was used as the sound processor of the Apple IIGS machine?

The latter is our great luck because Ensoniq themselves don´t give away any information, neither about their machines nor their chips. But fortunately Apple is offering at least the programming information in the Hardware Manual of the Apple IIGS (thanks to Henrik Gudat for providing me copies of the respective pages). 

Sad but true... These days one really calls for spam when publishing an email address on a website. But what the heck.

If you expect an answer please send plain text emails. HTML-formatted mails will be dumped automatically.

DOC - what's that?
The DOC is the sound engine of your SQ80 or ESQ-1 and was designed by Bob Yannes, who developed also the well-known SID6581 which was the sound generator of the famous Commodore 64 home computer back in the 80's. If you look closer at them both chips offer some parallels like
  • Oscillators are digitally generated based on phase accumulators
  • Amplification is done using multiplying D/A converters
  • A/D converter on chip
But since the DOC wasn't designed under such a timing pressure like the SID6581 and this led to certain differences. Let's have a closer look at this chip, which was the heart of all ancient Ensoniq machines:

The DOC consists of 32 time-multiplexed digital oscillators based on phase accumulators. The frequency resolution is 16bit whereas the sample resolution is 8bit unsigned, thus being $80 the zero level. Each oscillator is followed by a (digital) amplifier (which I assume to be a multiplying DAC) which is controlled via 8bit resulting in 48dB dynamic range. It's controlled through various registers which are explained in the following table.


The DOC contains common registers aswell as registers being individual for each oscillator which are listed here:

Common Registers

  • Oscillator Interrupt Register ($E0)
  • This register contains the status of the DOC interrupt request pin and the number of the oscillator which has generated the interrupt, if any. When an oscillator reaches the end of a wavetable (and the Enable Interrupt Bit for that oscillator has previously been set) the IRQ line and therefore bit 7 of the Oscillator Interrupt Register are set then together with the oscillator number in bits 5 to 1.
    Bit Function
    7 IRQ
    This bit is set to 0 if one of the 32 DOC oscillators generated an interrupt, otherwise it remains 1.
    6 reserved
    5-1 Number of interrupting oscillator
    0 reserved
    Oscillator Interrupt Register

  • Oscillator Enable Register ($E1)

  • Through this register the number of operating oscillators is controlled. To enable one or more oscillators one must multiply the desired number of oscillators (up to 32) by two and enter that number into this register, therefore any number from 2 to 64 is allowed and will enable the corresponding oscillators in sequential order. Low-numbered oscillators cannot be skipped in order to enable higher-numbered ones. Also, a minimum of one oscillator is always enabled, which is also the reset default.

    In the SQ80 this register is set to $2e so that 24 oscillators are enabled.

  • A/D Conversion Register ($E2)

  • The ADCR contains the output value of the internal successive-approximation ADC. An analogue input signal can be sampled (at which pin I´ll have to figure out) and the result of the conversion is stored in this register right after completing the conversion. Reading this register initiates the conversion process which will take 31 microseconds. If this register is read before the end of a started conversion process, the value will be lost and a new conversion will begin.

    The SQ80 uses this register for sampling pitch bend and modulation wheel, data input slider and the foot switch. However, it looks like the wheels being sampled more frequent or with a higher priority.

    In fact, this register is nothing more than access to a built-in AD7574 running in ROM-mode.

Individual Registers (0<=n<=31 represents oscillator number)

  • Frequency Registers (LSB: $00+n, MSB: $20+n)

  • The frequency of an oscillator is determine by the 16bit value formed out of MSB and  LSB. It doesn´t reflect the frequency of the oscillator but the speed at which the wave data is read from memory. The relationship between the frequency of the output signal (OF), the wavetable scan rate (SR) and the frequence ratio (FR) set by these registers is

    RES is the wave´s resolution set in the Wavetable Size Register.

    According to the Apple IIGS manual the scan rate SR is 894886kHz/(OSC+2). Who wants to do some calculations how the values are in the SQ80 just have a look at address $7000 to $7fff of ROMLOW where the values for all 127 possible semitones with a resolution of 10 cents per semitone are stored.

  • Volume Registers ($40+n)

  • The oscillator´s volume is stored here and the current wavetable data byte is multiplied by this 8bit value to obtain the oscillator´s final output level.
  • Data Registers ($60+n)

  • These are read-only registers and contain the wave's last played byte.
  • Wavetable Pointer Registers ($80+n)

  • These registers contain the starting page number of an oscillator´s wavetable. All wavetables must begin on a page boundary, i.e. the first byte of a page, and cannot wrap around to low memory addresses. The value in these registers is used for final address calculation referring to the selected page size, e.g. for a page size of 256 bytes all bits of this register are used. With 32k pages only bit 7 will be used for address calculation. Therefore, the maximum size of a single wave is limited to 32kB.

    In the SQ80 waveforms have individual sizes ranging from 256B up to 16kB.

  • Oscillator Control Registers ($a0+n)

  • All functions of each oscillators are controlled through this set of registers. Control includes which of eight optional external analogue multiplexer channels an oscillator will be routed to, whether or not and oscillator may generate an interrupt and the oscillator´s operating mode. The following modes are possible:

    Free-run mode

      An oscillator starts playing back a wave from its beginning and keeps on repeating it until the halt bit is set or a 0 is encountered in the wave data.
    One-shot mode
      Just like free-run mode but the wave is only played once, stopping at the end of the wave.
    Sync mode
      Sync mode is only possible between pairs of even and odd numbered oscillators, i.e. a lower even-numbered oscillator paired with a higher odd-numbered oscillator. When the even-numbered oscillator starts playing back its wavetable, its odd-numbered mate will be synchronized to it and begins its wavetable simultaneously.
      Since the SQ80 uses three oscillators per voice the (virtual) oscillator count is reordered to achieve the even/odd pairing.
    Swap mode
      Swap mode uses even/odd pairs of oscillators as explained above. The enabled oscillator runs in one-shot mode, when it reaches the end of its wavetable, it resets its accumulator to zero, sets its halt bit and clears the halt bit of its mate. With this method it its possible to play a 64kB sized wave without interrupt driven external control, but when using such methods it is theoretically possible to play back even longer waves.
Bit Function
7-4 Channel Address Bits
Only the low three bits are used for output routing by the SQ80, bit 7 is used for wave ROM addressing.
3 Interrupt Enable Bit
If set to one, interrupt flag and oscillator number will be set in the Oscillator Interrupt Register, so the DOC will assert the IRQ line on oscillator halt.
2-1 Oscillator Mode
The oscillator mode is selected by the following patterns:
Pattern Mode
00 Free-run
01 One-Shot
10 Sync
11 Swap

0 Halt Oscillator
This is a r/w bit and is set to 1 to halt the oscillator. Certain modes (one-shot, sync, swap) will halt the oscillator and set this bit automatically after completion. If an oscillator either is running or should be forced to run, this bit is cleared.

  • Wavetable Size Registers ($c0+n)

  • These registers control the size of an individual wavetable each oscillator will access. The size of a wavetable can vary from 256byte to 32kByte in 8 discrete steps as shown below.
Bit Function
7 reserved
This bit is indeed completely unused.
6 Extended Addressing
This bit is used for bank selection within a wave ROM. By default it's thought to switch between 64kB wave ROMs - in the SQ80 it depends on the type of (EP)ROMs used for wave storage.
5-3 Wavetable Size
The wavetables may extend up to 32kB in size, but in discrete steps only. Wavetables must also begin on a page boundary. Unused locations within a wavetable should begin with a minimum of eight zeroes, otherwise the oscillator will not halt when encountering these bytes and will interpret them as data.
Pattern Tablesize hex.
000 256 $0100
001 512 $0200
010 1024 $0400
011 2048 $0800
100 4096 $1000
101 8192 $2000
110 16384 $4000
111 32768 $8000

2-0 Address Bus Resolution
The wavetable is either played back using every byte or only intermittent bytes as data. These bits determine whether or not every byte is used during playback by selecting which accumulator bits are used for address calculation. For practical reasons this value has to be set to the same pattern as bits 5-3 thus resulting in A9 being the lowest used accumulator bits (highest depending on the wavetable size)
Highest Accu Bit
Lowest Accu Bit
(depending on Wavetable Size)

Looking inside your SQ80 you find the multisample zones at address $1000 of ROMLOW, every 16 bytes reflect one wave as offered to the sound programmer. Thus, such a zone is responsible for 8 semitones. From $14b0 onwards you find the raw sample data, 4 bytes being responsible for access of one raw waveform as stored in the rom. Byte 1 is the starting wavetable, Byte 2 the respective value for the Wavetable Size Register.

Differences in DOC revisions

Commonly, the 5503DOC appears in revision D, be it on Mirage, ESQ1/SQ80, or Apple IIGS. However, the first generation of Mirages uses a slightly different DOC.

Firstly, it does not include the ADC. In the first revision, the ADC (an AD7574, btw.) was externally applied, featuring its own address decoder that ensured that the DOC is limited to address offsets 0x00 to 0xe1, with the external ADC responding to offset 0xe2.

Furthermore, the original DOC shows explicitly that it only employs a single, time-shared DAC for volume and waveform output generation:

  • In a first phase, the volume output (pin 13) is sampled (triggered by pin 11), which then is fed back for waveform generation.
  • Consequently, the waveform output (pins 15/16) is also sampled using its own control signal (pin 12).
On rev. D, all this sampling and buffering is moved inside the DOC and only some minor current-to-voltage conversion and feedback takes place externally (cf. pins 11/VVref and 12/VOLFDBK on rev. D)

The differences can be easily spotted when comparing the 1984 and 1985 versions of the Mirage schematics. It should hence also be somewhat easy to convert an "old" Mirage to using a rev. D DOC.

Pinout of 5503DOC (rev D)
Thanks to Michael Käser I finally got the complete pinout of the Ensoniq DOC.
5503DOC pinout

Besides the obvious ones we have the follwing special pins:
  • CSRB: channel address strobe, shows validity of channel address outputs (CA0-3)
  • CAx: channel address outputs, used for external routing of the output signal to one of 16 possible audio channels
  • VVREF: volume voltage reference input(-5V)
  • VLFDBK: volume feedback
  • VOL-: adjustment of D/A output volume
  • WVREF: Wave Volume Reference
  • Sig+/Sig-: balanced analogue outputs
  • A/D: A/D converter input, signals must be in 0-2.5V range
  • BS: bank select, switch between 64kB banks of wave memory
  • Address and Data bus are used for both, communication with the CPU and accessing waveform memory
Ensoniq did not use all of the pins in the way one might expect from the pin naming, there are a few differences:
  • /RAS is used as /ALE for demultiplexing pins 23 to 30
  • CA3, normally selecting audio channels 8 to 15, is used (together with /CAS) for WaveROM selection.
  • E clock output serves as /CS for the WaveROMs
  • /IRQ is not used as CPU interrupt, thus using SWAP mode is quite impossible on the SQ80.