The FZ-1 is a 8086-based computer system. Thus, it separates memory and I/O
space. The latter is responsible e.g. for display and keyboard control
as well as button scanning and LED illumination. It's organized in I/O areas
of 8 Byte each resulting in 4 I/O addresses per slot (remember, the FZ-1 is
a 16Bit system).
This makes it pretty easy to stuff the necessary glue logic for interfacing
an IDE interface into free slots. Due to the nature of IDE we need to occupy
three slots. However, this is only the plain hardware part. Personally, I
don't like the idea of loading supplemental software from disk every time I
want to access the HD unit. Also, it would be fine to have some extra memory
for storing the HD directory, disk buffers etc. This is the more tricky
part, but this time the (otherwise accursed) early-Intel typical memory
segmentation is an advance: The FZ-1 only uses segments 000h (RAM), 100h
(Wave RAM) and F00h (ROM).
But Casio decided to use as few parts as
possible, thus, ROM occupies in fact segments 200h to F00h. So we need to
add another glue logic to break up this mega-segment (which mirrors every
100h) into single ones. So I decided to add 64kB of supplemental ROM plus
another 64kB of RAM which leads to the following schematics:
IDE-Interface for the FZ-1
Of course, this is a pretty easy approach allowing only PIO mode data
transfer which will allow abt. 500kB/s to 1MB/s transfer speed. But I'd say
loading a complete FZ-1 memory dump (4MB) in max. 8s is more than ok.